1. Field of the Invention
The present invention relates to integrated circuit design, more particularly, to a method for designing a semiconductor integrated circuit incorporating a memory macro.
2. Description of the Related Art
In designing structured ASICs (Application Specific Integrated Circuit) and FPGAs (Field Programmable Gate Array), limitations are imposed on the allowed maximum number of memory instances (memory regions used as memory arrays) integrated in an product integrated circuit, the allowed total maximum memory capacity (memory size) for the product integrated circuit and the allowed memory capacity of each memory instance are limited to predetermined values.
Conventionally, memory instances are usually assigned to memory macros in a one-to-one relationship, respectively, in the memory assignment of an ASIC, such as a cell base IC and a gate array. In addition, it is a well-known technique that a large memory macro is divided into a plurality of small memory macros, and the small memory macros are assigned to a plurality of memory instances with the small memory macros attached with peripheral circuits. According to this technique, the small memory macros are assigned to the memory instances, in a one-to-one relationship.
For an integrated circuit incorporating ten memory macros each having 512 word lines and 32 data lines, for example, only ten RAMs (random access memories) are allowed to be incorporated at a maximum, even when the capacity of each incorporated RAM is 512 words of 16 bits or less. In other words, the maximum number of memory instances allowed to be assigned is ten.
On the other hand, Japanese Laid Open Patent Application (JP-A 2005-085344) and Japanese Laid Open Patent Application (JP-A H07-084987) discloses integrated circuits in which a frequency-doubled clock is used to enhance the port number of the memory macros.
In the following, a description is given of an exemplary integrated circuit design for satisfying requests from the user, with reference to FIGS. 1, 2A and 2B, with an assumption that an integrated circuit product is designed in which two memory macros M1, M2 each having 512 word lines and 32 bit lines (such memory macros are referred to as 512 w*32 b memory macros, hereinafter) are integrated into a memory macro arrangement region 100 of the integrated circuit to be designed, as shown in FIG. 1.
In the conventional technique described above, only two memory instances are allowed to be assigned to the memory macros M1 and M2 in total, since only one memory instance is allowed to be assigned to one memory macro. In this case, three or more memory instances are not allowed be assigned to the two memory macros M1 and M2. Also, the memory size is predetermined for each memory macro. In the example of FIG. 1, the memory size of the memory macros M1 and M2 is 512 w*32 b, and a memory instance larger than this memory size is not allowed be assigned to the memory macros M1 and M2. It should be noted, however, that, when the memory macro M1 and/or M2 is allowed to be divided into two size-reduced memory macros with a size smaller than 512 w*32 b, the two size-reduced memory macros are allowed to be assigned to two memory instances I1 and I2.
On the other hand, the user often requests that memory macros of various configurations are integrated into the integrated circuit. No problem arises in a case when the user only requests a product with two 512 w*32 b memories. However, the user often requests that the product integrated circuit incorporates memories of memory sizes different from the predetermined value or that the number of memories integrated within the product integrated circuit is larger than the number of the memory macros. For example, the user may request the product integrated circuit to include the two 512 w*16 b memories. For such a request, as shown in FIG. 2A, memory instances I11 and I2 with 512 w*16 b are assigned to the memory macros M1 and M2, respectively. In this case, as shown in FIG. 2A, two 512 w*16 b regions, denoted by the numerals R1 and R2 in FIG. 2A, remain unused within the memory macros M1 and M2. That is, half of the total memory capacity of the product integrated circuit (here, 512 w*32 b) is not effectively used.
When the user requests a semiconductor integrated circuit incorporating the two 256 W*32 b memories as shown in FIG. 2B, on the other hand, 256 W*32 b memory instances I3 and 14 are assigned to the memory macros M1 and M2, respectively. This results in that two 256 W*32 b regions, denoted by the numerals R3 and R4 in FIG. 2B, remain unused in the memory macros M1 and M2, respectively. That is, similarly to the example shown in FIG. 2A, half of the total memory capacity of the integrated circuit to be designed is not effectively used.
As thus discussed, the conventional technique undesirably suffers from a drawback that the memory capacity of the overall integrated circuit is not efficiently used; parts of the memory macros, the total capacity of which is 512 w*32 b, for example, remain unused. Moreover, a memory instance can not to be added to the integrated circuit to be designed because of the lack of the memory macro, after memory instances are already assigned to all of the memory macros. For the case of the integrated circuit of FIG. 1, for example, the conventional art does not satisfy the use's requirement to add a third memory instance.